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SP5730
1.3GHz Low Phase Noise Frequency Synthesiser Preliminary Information
DS4877 issue 1.9 July 1999
Features
q Complete 1.3GHz single chip system for q q q q q q q q
Digital Terrestrial Television applications Selectable reference division ratio, compatible with (DTT) requirements Optimised for low phase noise, with comparison frequencies up to 4MHz No RF prescaler Selectable reference/comparison frequency output Four selectable I2C bus address I2C fast mode compliant and compatible with 3.3 and 5V logic levels Four switching ports ESD protection, (Normal ESD Handling procedures should be observed)
Ordering Information
SP5730A/KG/MP1S Sticks SP5730A/KG/MP1T Tape and Reel SP5730A/KG/QP1S Sticks SP5730A/KG/QP1T Tape amd Reel
Description
The SP5730 is a single chip frequency synthesiser designed for tuning systems up to 1.3GHz and is optimised for digital terrestrial applications. The RF preamplifier interfaces direct with the RF programmable divider, which is of MN+A construction so giving a step size equal to the loop comparison frequency and no prescaler phase noise degradation over the RF operating range. The comparison frequency is obtained either from an on-chip crystal controlled oscillator, or from an external source. The oscillator frequency, Fref, or phase comparator frequency, Fcomp, can be switched to the REF/COMP output providing a reference frequency for a second frequency synthesiser. The synthesiser is controlled via an I2C bus and is fast mode compliant. It can be hard wired to respond to one of four addresses to enable two or more synthesisers to be used on a common bus. The device contains four switching ports P0-P3.
Applications
q Digital Satellite ,Cable and Terrestrial tuning systems q Communications systems
SP5730
Preliminary Information
RF/COMP enable/select 12 BIT COUNT RF INPUT 8/9 3 BIT COUNT Lock fpd/2 15 BIT LATCH 2 BIT 5 BIT 2 BIT 2 BIT PUMP c/p mode disable CHARGE PUMP Osc CRYSTAL CRYSTAL CAP
REF DIVIDER
DRIVE
ADDRESS SDA SCL I 2 C BUS TRANSCEIVER
4 BIT LATCH & PORT INTERFACE
fpd/2 select
PORT P3 PORT P2 PORT P1PORT P0
Figure 1 Block diagram
CHARGE PUMP AGC CRYSTALIOUT CAP CRYSTAL VEEA SDA IFINB SCL IFIN PORT P3/LOGLEV IVCCA PORT P2 QOUT PORT P1
1
16
DRIVE VCCB VEE VCODIS RF B VCOINPUT RF A VCOINPUT VCC VEEB REF/COMP PSCAL ADDRESS PSCALB PORT VCCC P0
VEEC
SL1711B
MP16 Figure 2 Pin connections top view
MP16 & QP16
2
Preliminary Information
Electrical Characteristics
SP5730
o o Tamb= -40 C to 85 C, VCC= 4.5 to 5.5V These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated.
Characteristic Supply current RF input voltage RF input voltage RF input impedance SDA, SCL Input high voltage Input low voltage Input high voltage Input low voltage Input high current Input low current Leakage current Hysteresis SDA output voltage
Pin Min
Value Typ
Units Max 20 300 300 mA mVrms mVrms
Conditions
13,14 13,14 13,14 4, 5
12.5 40
100 MHz - 1.3GHz, see Figure. 4 50MHz - 100MHz, see Figure 4 See Figure. 5
3 0 2.3 0
5.5 1.5 3.5 1 10 10 10 0.4
V V V V A A A V V V kH
5V I C logic selected 5V I C logic selected 3V3 I C logic selected 3V3 I C logic selected Input voltage =Vcc Input voltage = Vee Vee = Vcc
2 2 2
2
4
0.4 0.6 400
Isink = 3mA Isink = 6mA
SCL clock rate Charge pump output current Charge pump output leakage Charge pump drive output current Crystal frequency Recommended crystal series resistance External reference input Frequency External reference drive level
5 1
See Table 6 Vpin1 = 2V
1
3
10
nA
Vpin1 = 2V, Vcc = 5V, +25C
16
0.5
mA
Vpin16 = 0.7V
2,3
2 10
20 200
MHz
See Figure 3 for application 4 MHz "parallel resonant" crystal. Sinewave coupled through 10 nF blocking capacitor Sinewave coupled through 10 nF blocking capacitor
3
2
20
MHz
3
0.2
0.5
Vpp
3
SP5730
Electrical Characteristics (continued)
o o Tamb= -40 C to 85 C, Vcc= 4.5 to 5.5V
Preliminary Information
These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Buffered REF/COMP output output amplitude output impedance Phase detector Comparison frequency Equivalent phase noise at phase detector RF division ratio Reference division ratio Output ports P0 - P3 sink current Leakage current Address Select Input high current Input low current Logic level select Input high level Input low level Input current 6-9 2 10 10 1 -0.5 6 3 0 -10 Vcc 1.5 10 V V A mA mA mA A Pin Min 11 0.35 250 4 Vpp MHz Value Typ Units Max AC coupled 0.5-20MHz Enabled by bit RE= 1 See note 2 Conditions
dBc/Hz -152 -158 56
SSB, within loop bandwidth Fcomp = 2MHz Fcomp = 125kHz
32767 See Table 1 See Note 1 Vport = 0.7 Vport = Vcc See Figure 4 Table 3 Vin = Vcc Vin = Vee See note 3 5V I2C logic selected, or open circuit 3V3 I2C logic selected Vin = Vee to Vcc
Notes: 1. Output ports high impedance on power up, with data, clock, and enable at logic `0' 2. If the REF/COMP output is not used, the output should be left open circuit or connected to Vcc, and disabled by setting RE = 0 3. Bi-directional port. When used as an output, the input logic state is ignored. When used as an input the port should be switched in to high impedance (off) state.
4
Preliminary Information
Absolute Maximum Ratings
All voltages are referred to Vee at 0V Characteristic Min Supply voltage, Vcc -0.3 RF input voltage All I/O port DC offsets -0.3 SDA and SCL DC offset -0.3 Storage temperature -55 Junction temperature QP16 thermal resistance, chip to ambient chip to case Power consumption at Vcc = 5.5V ESD protection 2 Max 7 2.5 Vcc+0.3 6V +150 150 80 20 83 Units V Vpp V V o oC C C/W C/W mW kV Conditions Transient Differential
SP5730
All ports off mil std 883 latest revision method 3015 class 1
Functional Description
The SP5730 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. It can also be operated with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (DTT) receivers The block diagram is shown in Figure 2. The RF input signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider, which is of MN+A architecture, where the dual modulus prescaler is 8/9, the A counter is 3-bits, and the M counter is 12 bits. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in Table 1. The output of the phase detector feeds a charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter, integrates the current pulses into the varactor line voltage. The programmable divider output Fpd divided by two can be switched to port P0 by programming the device into test mode. The test modes are described in Table 4.
Programming
The SP5730 is controlled by an I2C data bus and is compatible with both standard and fast mode formats and with I2C data generated from nominal 3.3V and 5V sources. The I2C logic level is selected by the bi-directional port P3/LOGLEV. 5V logic levels are selected by connecting P3/LOGLEV to Vcc or leaving open circuit and 3.3V by connecting to ground. If this port is used as an input the P3 data should be programmed to high impedance. If used as an output 5V logic only levels can be used and in this case the logic state imposed by the port on the input is ignored. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The synthesiser can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. Table 2 illustrates the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C bus system. Table 3 shows how the address is selected by applying a voltage to the `address' input.
5
SP5730
When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. Write mode With reference to Table 2, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Byte 4 and byte 5 control the reference divider ratio, see Table 1, charge pump setting, see Table 6, REF/COMP output, seeTable 7, output ports and test modes, see Table 4. After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic `0' indicating byte 2, and a logic `1' indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without readdressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. Read mode When the device is in read mode, the status byte read from the device takes the form shown in Table 2. Bit 1 (POR) is the power-on reset indicator, and this is set to a logic `1' if the Vcc supply to the device has dropped below 3V (at 25C), e.g. when the device is initially turned ON. The POR is reset to `0' when the read sequence is terminated by a STOP command. When POR is set high this indicates that the programmed information may have been corrupted and the device reset to power up condition. Bit 2 (FL) indicates whether the device is phase locked, a logic `1' is present if the device is locked, and a logic `0' if the device is unlocked.
Preliminary Information
Programmable features
RF programmable divider Function as described above Reference programmable divider Function as described above. Charge pump current The charge pump current can be pro grammed by bits C1-C0 within data byte 5, as defined in Table 6. Test mode The test modes are invoked by bits REB. RS, T1 and T0 as described in Table 4. Reference/Comparison frequency output The reference frequency Fref or comparison frequency Fcomp can be switched to the REF/COMP output, function as defined in Table 7. RE and RS default to logic `I' during device power up, thus enabling the comparison frequency Fcomp at the REF/COMP output.
6
Preliminary Information
R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X = don't care Table 1 Reference division ratio R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Ratio 2 4 8 16 32 64 128 256 Illegal state 5 10 20 40 80 160 320 Illegal state 6 12 24 48 96 192 384 Illegal State 7 14 28 56 112 224 448
SP5730
MSB Address Programmable divider Programmable divider Control Data Control Data 1 0 27 1 C1 1 214 26 T1 C0 0 213 25 T0 RE 0 212 24 R4 RS 0 211 23 R3 P3 MA1 210 22 R2 P2 MA0 29 21 R1 P1
LSB 0 28 20 R0 P0 A A A A A Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
Table 2 Write data format (MSB is transmitted first)
7
SP5730
MSB 1 POR
Preliminary Information
LSB 1 0
Address Status byte
1 FL
0 0
0 0
0 0
MA1 0
MA0 0
A A
Byte 1 Byte 2
Table 2 Read data format (MSB is transmitted first) A MA1,MA0 14 0 2 -2 R4-R0 C1, C0 RE RS T1-T0 P3-P0 POR FL : : : : : : : : : : : Acknowledge bit Variable address bits (see Table 3) Programmable division ratio control bits Reference division ratio select (see Figure 3) Charge pump current select (see Figure 6) REF/COMP output enable REF/COMP output select when RE=1 (see Figure 2) Test mode control bits P3 - P0 port output states Power on reset indicator Phase lock flag
MA1 0 0 1 1
MA0 0 1 0 1
Address input voltage level 0 - 0.1Vcc Open circuit 0.4Vcc - 0.6Vcc # 0.9Vcc - Vcc
# Programmed by connecting a 30k 5% resistor between pin 10 and Vcc Table 3 Address selection
RE.RS 0 1 X X X
T1 0 0 0 1 1
T0 0 0 1 0 1
Test mode description Normal operation Normal operation Port P0 = Fpd/2 Charge pump sink.* Status byte FL set to logic `0' Charge pump source * Status byte FL set to logic `0' Charge pump disabled * Status byte FL set to logic `1'
*clocks need to be present on crystal and RF inputs to enable charge pump test modes and to toggle Status byte bit FL X = Dont Care Table 4 Test modes
8
Preliminary Information
SP5730
C1 byte 5, bit 1 0 0 1 1
C0 byte 5, bit 2 0 1 0 1 Min +- 116 +- 247 +- 517 +- 1087
Current in A Typ +- 155 +- 330 +- 690 +- 1450 Max +- 194 +- 412 +- 862 +- 1812
Table 6 Charge pump current
2 68pF 150pF
SP5730
3
Figure 3 XTAL oscillator application
RE 0 0 1 1 X = don't care
RS 0 1 0 1
REF/COMP OUTPUT High impedance High impedance Test mode enabled, see Figure 5 Fref selected Fcomp selected
Table 7; REF/COMP output
9
SP5730
Preliminary Information
300
37.5
25
12.5
50
100
500
1000 Frequency (MHz)
1300
1500
Figure 4 Typical RF input sensitivity
+j1 +j0.5 +j2
+j0.2
+j5
0
0.2
0.5
1
2
5 X
-j0.2
-j5
-j0.5 -j1
-j2
FREQUENCY MARKERS AT 1.3GHz, 1.8GHz, 2.3GHz, 2..8GHz 50MHz, 500Mhz, 1GHz 1.3GHz
Figure 5 RF input impedance
10
5V
C42 C43 C49 C33 C41 C44 C47 100pF 100nF 100pF 100pF100nF 100nF 4u7F
J1 5 WAY 0.1" HEADER
5V Synth
1 2 3 4 5
+5V 0V +30V 0V 5V Synth
C50 C51 C52 100nF 100pF 4u7F C34 100nF R8 22K
Preliminary Information
R7 13K
C32 R19 68pF R9 IC2 16K C31 15nF
Varactor Line 2
1K R10 1K C39 2.2nF
Varactor Line
1 Charge Pump Drive Output 16 Phase Comparator 2 Xtal Cap Vee 15 Osc 3 Xtal RF Input 14 Programmable Divider PSOUTB
C60 150pF R20 0R
T1 BCW31
C30
82pF X1
5V Synth 4 SDA 13 RF Input 5 Vcc I2C Bus Interface 6 5V Synth 7
R16 10K
4MHz
J3
SCL5 GND 5V0 SDA5 SCL 12
6 5 4 3
PSOUT
5V Synth Ref/Comp 11
I2C BUS
P3/LL
P2
Address
10
C37 C38 100pF 100pF
8
SP5769
P1
P0
9
LOSEL
SP5730
Figure 6 evaluation board schematic
11
SP5730
Preliminary Information
Figure 7 Evaluation board (top view)
Figure 8 Evaluation board (bottom view)
12
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